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Successfully powering up a system can be tricky. So can powering one off. Timing, order of events, and power levels need to be just right for proper system functionality and stability. Power sequencing can also prevent unnecessary current draw while portions of the design sit idle, waiting for prerequisite systems to be powered. Some FPGAs may require more than ten rails, which if sequenced using discrete components, could introduce extra power and board space overhead.
Demo Board Power Sequencing Design in GreenPAK 5
Using Silego’s GreenPAK™ family of devices, it is easy to implement custom power sequencing designs in an extremely small area, using minimal power and board space. When paired with the tiny, ultra-low RDSON GreenFET™ Integrated Power Switch, power sequencing with Silego is an incredibly efficient solution.
Often in various combinations in a single system, some common methods for power sequencing include:
Example 1. Fixed Delay Sequencing
One method for sequencing multiple sub-systems is to allot a fixed amount of time for each start-up sequence. This is appropriate for systems which do not feature a Power Good signal. Finding a discrete solution with the exact delay timings needed can take hours, but with GreenPAK’s configurable logic and timing resources, developing a custom system is easy.
|Example 1. Timing Diagram||Example 1. GreenPAK Implementation|
Example 2. Sequencing with Power Good
Many ICs have the ability to produce a Power Good (PG) signal once the respective systems have finished their start-up routine. This can be useful in systems where start-up time is not fixed and may depend on multiple variables.
|Example 2. Timing Diagram||Example 2. GreenPAK Implementation|
Example 3. Power Sequencing with I2C Acknowledge
Another option in programmable systems with I2C is to send a command to the power sequencer, in this case GreenPAK, to let it know start-up was completed successfully. Using GreenPAK's I2C virtual inputs, it is easy to treat an I2C command just like a digital Power Good signal.
|Example 3. Timing Diagram||Example 3. GreenPAK Implementation|
Example 4. Power Sequencing with Voltage Sensing
To ensure system stability, many SOCs, DSPs, and FPGAs require a minimum voltage for startup. Monitoring the power level of a rail can be done simply using GreenPAK’s configurable analog comparators.
|Example 4. Timing Diagram||Example 4. GreenPAK Implementation|