AN-1042 Remote Control IR Reciever/Decoder

This design is a configurable remote control infrared receiver and decoder. It also performs address and command comparison, and provides a matching true indicator. It is designed compliant with the NEC protocol, and can be configured for any 8-bit address and remote control command. The NEC protocol uses “pulse distance” encoding of the bits. Each pulse is a 560µs long pulse burst with 38kHz carrier (about 21 periods). A logic "1" takes 2.25ms to transmit, while a logic "0" is only half of that, being 1.125ms. The typical carrier duty-cycle is 1/4 or 1/3 for optimum range and power considerations. Figure 1 shows a typical pulse train of the NEC protocol. LSB is transmitted first. A message is started by a 9ms AGC burst, which is used to set the gain of some IR receivers that might require it. This AGC burst is then followed by a 4.5ms space, which is then followed by the Address and Command.

Address and Command are transmitted twice. The second time all bits are inverted and can be used for verification of the received message (redundancy).

The total transmission time is constant because every bit is repeated with its inverted length. The range of addresses and commands can be extended to 16bits each by not using the inverted values (Extended protocol). A command is transmitted only once, even when the key on the remote control remains pressed. Every 110ms a repeat code is transmitted for as long as the key remains pressed. This repeat code is simply a 9ms AGC pulse followed by a 2.25ms space and a 560µs burst. More information on the protocol is available at:

NEC protocol

Figure 1. NEC protocol

Extended NEC protocol

Figure 2. Extended NEC protocol

In this design implementation we convert a serial input data stream to parallel, and then compare the values against stored addresses and commands. To convert input data from serial to parallel we need to first extract the clock signal, enable signal conversion, and then the data.

IR Receiver Circuit Design

As can be seen in Figure 3, to prepare data for conversion one DFF, two 3-bit LUT, two 2-bit LUTs, three CNT/DLYs, RC OSC, POR, three PINs were used.

Preparing Data for Conversion

Figure 3. Preparing Data for Conversion

Data start is detected by using components connected in the following sequence: 2-bit LUT1 and CNT0/DLY0 detect 9ms from signal sequence, while 2-bit LUT2 and CNT1/DLY1 detect an additional 4.5ms from signal sequence.

Clock signal (CLOCK_OUT) is generated by: 3-bit LUT0, CNT2/DLY2/FSM0 and 3-bit LUT1 (uniting the result of start sequence: 9ms and 4.5ms) and DFF0. Enable signal (nCSB_OUT) is generated by the components that detect start signal and DFF0. As can be seen in Figure 4, the complete IR receiver is requires additional components such as: one S2P, three DCMP/PWMs, two DFFs, two 3-bit LUTs, DFF, Pipe delay, and a TSOP4838 (PIN diode/preamp, demodulator module).

IR Receiver Circuit Design

Figure 4. IR Receiver Circuit Design

The input data stream is converted from serial to parallel by using S2P block, and the output values are compared with predetermined (configurable) stored values using DCMP0, DCMP1, and DCMP2. DCMP0 and DCMP2 perform address comparison and the combination of 3-bit LUT1 and DFF1 stores the address comparison result. DCMP1 performs command comparison and the combination of 3-bit LUT2 and Pipe delay stores the command comparison result.

IR Receiver Circuit Analysis

When this device is turned on the OUT (PIN 12) is set LOW, IR_IN (PIN6) – HIGH, CLOCK_OUT (PIN5) – LOW and OUT_LATCH_EN (PIN3) – as defined by user. To enable device operation, OUT_LATCH_EN has to be kept HIGH. When the button on the remote control is pressed the data stream will appear on IR_IN (PIN6). Then the sequence is decoded by the device and if the address and command match the stored values, the OUT (PIN12) will go HIGH. If the address and command do not both match – OUT(PIN12) will stay LOW. If PIN3 (OUT_LATCH_EN) is LOW, the saved result is cleared. The functionality waveforms that describe the device operation are shown in Figures 5, 6, 7 and 8. This device and completed PCB were tested and are shown in Figures 9, 10, and 11.

Conversion of the data stream from Serial to Parallel

Figure 5. Conversion of the data stream from Serial to Parallel
Channel 1 (yellow/top line) – PIN#12 (nCSB_OUT);
Channel 2 (light blue/2nd line) – PIN#5 (CLOCK_OUT);
Channel 3 (magenta /bottom line) – PIN#6 (IR_IN)

SLG46140V IR Receiver Circuit

Figure 6. IR Receiver Bit Sequence
Channel 1 (yellow/top line) – PIN#12 (OUT);
Channel 2 (light blue/2nd line) – PIN#5 (CLOCK_OUT);
Channel 3 (magenta /bottom line) – PIN#6 (IR_IN)

Address and Command match

Figure 7. Address and Command match
Channel 1 (yellow/top line) – PIN#12 (OUT);
Channel 2 (light blue/2nd line) – PIN#5 (CLOCK_OUT)
Channel 3 (magenta /bottom line) – PIN#6 (IR_IN)

Command NOT matching

Figure 8. Command NOT matching
Channel 1 (yellow/top line) – PIN#12 (OUT);
Channel 2 (light blue/2nd line) – PIN#5 (CLOCK_OUT);
Channel 3 (magenta /bottom line) – PIN#6 (IR_IN)

IR Receiver Typical Application Circuit

Figure 9. IR Receiver Typical Application Circuit

IR Receiver PCB Layout

Figure 10. IR Receiver PCB Layout

Complete design

Figure 11. Complete design


A remote control IR receiver, decoder, comparator can be easily implemented using a GreenPAK 2. It is a very useful solution when mostly just one configurable address and command are needed. It has low power consumption and few external components.


Updated version published as AN-1184 Remote Control IR Reciever/Decoder

About the Author

Name: Oleg Gorodechny

Background: Oleg Gorodechny received Bachelor’s degree in “Computer Science” in 2009 and Master’s degree in “Information Control Systems and Technologies” in 2011 from Lviv Polytechnic National University. Since 2011 he has been working as a design engineer and in 2013 he began to work for Silego Technology Inc. as an application engineer. Currently he is making analog circuit designs and working with their application.




See full list of Application Notes