AN-1079 High Speed Level Shifter With Dual Supply GreenPAK

Designs are growing in complexity, including different ICs in the same design which operate in different voltage domains. SOCs continue to lower their power supply voltage, while sensors tend to stay at higher voltages. Logic levels compatible at 5V are incompatible with their 3.3V counterparts. Multiple power rails increase the need to have interface chips that translate voltages from one level to another with sufficient speed.

Level Shifter with LVDI

There are many ways to interface with different voltages levels in PAK. See Silego’s AN-1063 to see a level shifting technique using external coupling circuitry not discussed here. One way to detect low level logic levels is by using the Low Voltage Digital Input (LVDI) PIN option available in PAK. Setting a pin to LVDI lowers the VIH to ~1.2V, even with high Vdd voltage. Thus, low level inputs can be detected while outputs maintain a high voltage swing. However, throughput is limited when using the LVDI because the asymmetry of the LVDI circuitry causes propagation delay skew of ~700ns.

Dual Supply GreenPAK

The Dual Supply GreenPAK, SLG46621V, includes two voltage rails with integrated level shifters to make interfacing two levels easy while maintaining high speed. Vdd (PIN1) powers the main circuitry and the I/O for PINs 2-10. Vdd2 (PIN14) powers the I/O circuitry for PINs 12-20.

The secondary Vdd is labeled Vdd2 and automatically translates between the PINs powered by Vdd2 and the rest of the chip.

For I/O connected to Vdd2, the LVDI settings do not need to be used when interfacing different voltage domains. Thus, the Vdd2 is powered by the lower voltage rail to match the threshold specs while avoiding the propagation delay from the LVDI.

Throughput Comparisons

A comparison is shown graphically in Figure 1 visualizing the increase in throughput by using the Dual Supply GreenPAK’s internal level shifters as compared to an LVDI configuration. The constraint to determine the maximum throughput is determined using two rules: the output duty cycle must stay between 40%-60% and the output voltage must be greater than 90% of typical VOH.

Input PIN Comparison

Figure 1. Input PIN Comparison

The LVDI, Shift-up, and Shift-down configurations are explained below. LVDI: Both Vdd and Vdd2 are set to 5V, while the input signal ranges from 0V to 1.8V. The input pin is configured as below, shown in Figure 2.

Shift-Up: To shift an input signal up in the Dual Supply GreenPAK, configure the input supplied on Vdd2 as a Digital Input with/without Schmitt Trigger. Match Vdd2 to the level of the lower voltage input signal. For these tests, Vdd is set to 5V and Vdd2 along with the input. 

PIN 6 Configuration

PIN 13 Configuration

Figure 2. LVDI Configuration Settings

Figure 3. Shift-up Configuration Settings

Shift-Down: Conversely, shifting down is just as easy. Choose input PINs 2-10 with the higher Vdd while the shifted-down output on PINs 12-20.

CH1 (Yellow/Top line) – PIN#03 5V Input

CH2 (Green/ 2nd line) – PIN#20 1.8V Output

Vdd1 = 5V, Vdd2 = 1.8V

Level-Shift Response at 15MHz

Figure 4. Level-Shift Response at 15MHz

Test Data

These quick tests were done using twoindependent power supplies, a frequency generator and the SLG46621V programed in socket. The input signal was connected via a shielded SMA cable to the GPAK socket. Table 1 shows the input configurations and Table 2 shows the results used in this application note.

Test Configurations

Table 1. Test Configurations

Test Results

Table 2. Test Results

Conclusion

The throughput for a LVDI configuration is much lower in all cases due to the propagation delay through the LVDI circuitry, thus a Dual Supply GreenPAK is better equipped to handle high speed signals between different voltages.

About the Author

Name: Luke Thomas

Background: Luke earned a B.S. in Electrical Engineering with a concentration in Computer Engineering from Grove City College. Presently he is working with Configurable Mixed Signal ICs (CMICs) and their applications.

Name: Gino Castillo

Background: Gino is pursuing a B.S. in Bioengineering with a minor in Electrical Engineering at Santa Clara University. Presently he is working with Configurable Mixed Signal ICs (CMICs) and their applications.

Contact: appnotes@silego.com

 

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